Workshop 18-DRNoC

International Workshop on Dynamic Reconfigurable Network-on-Chip

(DRNoC 2015)


As part of

The International Conference on High Performance Computing & Simulation (HPCS 2015) or

July 20 – July 24, 2015

The Hilton Amsterdam Hotel

Amsterdam, The Netherlands

Extended Paper Submission Deadline: April 24, 2015

Submissions could be for full papers, short papers, poster papers, or posters


Network-on-chip (NoC) has been recently proposed for SoC applications design to achieve better performance and lower energy consumption when compared to conventional on-chip bus architectures. Recently, there has been a great deal of interest in the development of run-time approaches for reconfigurable NoC. These approaches provide techniques that allow NoC to autonomously adapt its structure and its behavior to system changes.

Emerging SoCs (System-on-Chip, such as those for mobile systems, are typically battery-powered systems and have to support a wide range of streaming applications such as video and audio. Network-on-chip has been recently proposed for SoCs applications design to achieve better performance and lower energy consumption when compared to conventional on-chip bus architectures.

Several approaches have been proposed to deal with NoCs and can be classified into two main categories, design-time approaches and run-time approaches. Design-time approaches are generally tailored an application domain or a specific application by providing an application- specific NoC. All parameters, such as the on-chip interconnect architecture (i.e., topology), routing, and switching schemes, are defined at design time. However, NoC should be scalable and adaptive to support various applications by selecting the most suitable parameters based on the requirements of the current application and system conditions.

Recently, there has been a great deal of interest in the development of run-time approaches for reconfigurable NoCs. These approaches provide techniques that allow NoCs to autonomously adapt its structure and their behavior during the course of their operation (i.e., in runtime). For example, the number of VCs (virtual channels) and the buffer size per VC can be dynamically adjusted based on the traffic load and network status.

DRNoC 2015 workshop is intended to serve as a forum and bring together the researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of dynamic reconfigurable NoCs. It will cover current and new approaches and relevant activities in the design, analysis, and evaluation of techniques for dynamic reconfigurable NoCs.

The DRNoC Workshop topics of interest include (but are not limited to) the following:

  • Topologies reconfiguration for NoCs

  • Three-Dimensional NoC Design

  • Reliability, scalability, availability, and fault tolerance

  • Mapping and scheduling of tasks into NoCs

  • Self-reconfiguration and self-optimization of NoCs

  • Bio-inspired techniques for reconfigurable NoCs

  • Analytical evaluation methods for designing reconfigurable NoCs

  • Area, energy, and performance evaluation

  • Tools for design space exploration of reconfigurable NoCs

  • Cases studies and FPGA-based implementation of reconfigurable NoCs


You are invited to submit original and unpublished research works on above and other topics related to Dynamic Reconfigurable Network-on-Chip. Submitted papers must not have been published or simultaneously submitted elsewhere. For Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column IEEE formatted pages, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s). Short papers (up to 4 pages), poster papers and poster (please refer to for posters submission details) will also be accepted. Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments.

Submit a PDF copy of your full manuscript via email to the Workshop organizers at, and Submissions will be acknowledged within 48 hours.

Only PDF files will be accepted, sent as email attachment to the organizers emails. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, significance, technical clarity, and presentation. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. At least one of the authors of each accepted paper will have to register and attend the HPCS 2015 conference to present the paper at the workshop.


Accepted papers will be published in the Conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2015 Conference web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is projected to be included in the IEEE Digital Library and indexed in all major indexing services accordingly.

If you have any questions about paper submission or the workshop, please contact the workshop organizers.


Paper Submissions: ----------------------------------------- April 24, 2015

Acceptance Notification: ----------------------------------- May 04, 2015

Camera Ready Papers and Registration Due by: -------- May 14, 2015

Conference Dates: ------------------------------------------ July 20 – 24, 2015


Mohamed Bakhouya

International University of Rabat

Technopolis Rabat-Shore, 11100, Sala el Jadida, Morocco

Phone: +212 648 452 702

Fax: +212



Masoud Daneshtalab

University of Turku, Finland and KTH Royal Institute of Technology, Sweden

Phone: +358-23 33 69 41



Masoumeh Ebrahimi

KTH Royal Institute of Technology, Sweden and University of Turku, Finland

Phone: +46 879 04 180

Email: ,

Jaafar Gaber

University of Technology of Belfort-Montbeliard

90010 Belfort Cedex, France

Phone: +33 (0)3 84 58 32 52

Fax: +33 (0) 3 84 58 33 42



International Program Committee*:

All submitted papers will be rigorously reviewed by the workshop technical program committee members following similar criteria used in HPCS 2015.

  • Nader Bagherzadeh, University of California-Irvine, USA

  • Julien Bourgeois, University of France-Comte, France

  • Eugen Dedu, University of Franche-Comté, France

  • Tarek El-Ghazawi, George Washington University, D.C., USA

  • Klaus Hofmann, Darmstadt University of Technology, Germany

  • Miaoqing Huang, University of Arkansas, Arkansas, USA

  • Farshad Khunjush, Shiraz University, Iran

  • Lauri Koskinen, Aalto University, Finland

  • Sergio Lopez-Buedo, Universidad Autonoma de Madrid, Spain

  • Pascal Lorenz, University of Haute Alsace, France

  • Pejman Lotfi-Kamran, EPFL, Switzerland

  • Samia Loucif, AlHosn University, UAE

  • Mehdi Modarressi, Tehran University, Iran

  • Vikram Narayana, George Washington University, D.C., USA

  • Smail Niar, University of Valenciennes, France

  • Maurizio Palesi, Kore University, Italy

  • Sven-Arne Reinemo, Simula, Norway

  • Maxime Wack, University of Technology of Belfort-Montbeliard, France

  • Xiaohang Wang, Guangzhou Institute of Advanced Technology, China

  • Haoyuan Ying, Darmstadt University of Technology, Germany

For information or questions about Conference's paper submission, tutorials, posters, workshops, special sessions, exhibits, demos, panels and forums organization, doctoral colloquium, and any other information about the conference location, registration, paper formatting, etc., please consult the Conference’s web site at URL: or or contact one of the Conference's organizers.

  • Routing algorithms, switching techniques, and flow control schemes