Workshop 23-AASC

International Workshop on Architecture-Aware Simulation and Computing
(AASC 2015)


As part of
The International Conference on High Performance Computing & Simulation (HPCS 2015)

July 20 – July 24, 2015
The Hilton Amsterdam Hotel
Amsterdam, The Netherlands 

Extended Submission Deadline: April 15, 2015

Submissions could be for full papers, short papers, poster papers, or posters

To keep pace with the performance increase predicted by Moore's Law, homogeneous/heterogeneous processor aggregates have been extensively adopted both at the High Performance Computing (HPC) and at the embedded system domains. However, such steadily increase (often attained by simply scaling the number of computing cores within a chip) has been threatened by several architectural and technological constraints: limited parallelization opportunities (either at data, task, or even at instruction level); reduced memory throughput and complex cache hierarchies; limited communication bandwidth; thermal, power and energy constraints, etc. 

On the other hand, the prevailing heterogeneous computing architectures, often integrating different types of coprocessors (e.g., Intel Xeon Phi) and accelerator components (e.g., GPUs, FPGAs, etc.) has introduced complex challenges to efficiently program and implement HPC applications. 

On the embedded domain, different compromises to cope with strict energy efficiency requirements have been demanded. Despite the several different approaches that have been considered either at the processor architecture level (e.g., ARM big.LITTLE clusters) or at the coprocessor/accelerator level (e.g., mobile GPUs, reconfigurable SoCs, etc.), complex challenges are still posed in order to attain the ever increasing performance levels that have also been claimed in this specific domain. 

Therefore, it is widely recognized that next generation HPC and embedded systems can only benefit from the hardware’s full potential if both processor and architecture features are taken into account at all development stages - from the early algorithmic design to the final implementation stage. 

The AASC workshop strives to address all aspects related to these issues, including, but not limited to:

  • Hardware-aware compute/memory-intensive simulations of real-world problems in computational science and engineering domains (e.g., applications in electrical, mechanical, physics, geological, biological, or medical engineering).
  • Architecture-aware approaches for large-scale parallel computing, including scheduling, load-balancing and scalability studies.
  • Architecture-aware parallelization on HPC platforms, including multi-/many-core architectures comprising coprocessor/accelerator components (e.g., Intel Xeon Phi, GPUs, FPGAs, etc.).
  • Architecture-aware approaches for energy-efficient implementations of HPC or embedded applications (e.g., ARM big.LITTLE, mobile GPUs, reconfigurable SoCs, etc.).
  • Programming models and tool support for parallel heterogeneous platforms (e.g., CUDA, OpenCL, OpenACC, etc.).
  • Software engineering, code optimization, and code generation strategies for parallel systems with multi-/many-core processors.
  • Performance and memory optimization tools and techniques (including cache optimization, data reuse, data streaming, etc.) for parallel systems with multi-core processors.

You are invited to submit original and unpublished research works on above and other topics related to Architecture-Aware Simulation and Computing.  Submitted papers must not have been published or simultaneously submitted elsewhere.  Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and email addresses.  Please, indicate clearly the corresponding author and include up to 6 keywords from the above list of topics and an abstract of no more than 400 words.  The full manuscript should be at most 8 pages using the two-column IEEE format.  Additional pages will be charged additional fee.  Short papers (up to 4 pages), poster papers and posters (please refer to  for the posters submission details) will also be accepted for submission. In case of multiple authors, an indication of which author(s) is responsible for correspondence must be indicated. Please include page numbers on all submissions to make it easier for reviewers to provide helpful comments. 

Submit a PDF copy of your full manuscript to the Workshop submission site at  Acknowledgement will be sent within 48 hours of submission. 

Only PDF files will be accepted.  Each paper will receive a minimum of three reviews.  Papers will be selected based on their originality, relevance, contributions, technical clarity and presentation.  Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. Authors of accepted papers must guarantee that their papers will be registered and presented at the workshop. 

Accepted papers will be published in the conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2015 web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is to be published as ISBN proceedings by the IEEE and will be available online through IEEE Digital Library and indexed by major indexing services accordingly (e.g., EI indexing). 

If you have any questions about paper submission or the workshop, please contact the workshop organizers. 

Paper Submissions (Open): --------------------------------- April 15, 2015
Acceptance Notification: ------------------------------------  April 30, 2015
Camera Ready Papers and Registration Due by: ---------  May 14, 2015
Conference Dates:  ------------------------------------------- July 20 – 24, 2015


Nuno Roma
    Department of Electrical and Computer Engineering 
    INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Portugal
    Phone: +351 21 310 0311
    Fax:     +351 21 314 5843

João Cardoso
   Department of Informatics Engineering (DEI)
   Faculdade de Engenharia, Universidade do Porto, Portugal
   Phone: +351 91 662 9046

International Program Committee*:  
All submitted papers will be rigorously reviewed by the workshop technical program committee members following similar criteria used in HPCS 2015.  
  • Giovanni Agosta, Politecnico di Milano, Italy
  • Vanderlei Bonato, University of Sao Paulo, Brazil
  • Henri-Pierre Charles, CEA, France
  • Ray Cheung, City University of Hong Kong, China
  • Diana Goehringer, Ruhr-University Bochum, Ger­ma­ny
  • Dominic Hillenbrand, NVIDIA, Japan
  • Christian Hochberger, Darmstadt University of Technology, Germany
  • Waqar Hussain, Tampere University of Technology, Finland 
  • Dirk Koch, University of Manchester, United Kingdom
  • Gianluca Palermo, Politecnico di Milano, Italy
  • Pedro Tomás, INESC-ID, IST, Universidade de Lisboa, Portugal
  • Hans Vandierendonck, Queen's University Belfast, United Kingdom
  • Ana Lucia Varbanescu, TU Delft, The Netherlands
  • Markus Weinhardt, Osnabrueck University of Applied Sciences, Germany
  • Stephan Wong, TU Delft, The Netherlands
  • TBA, TBA

For information or questions about Conference's paper submission, tutorials, posters, workshops, special sessions, exhibits, demos, panels and forums organization, doctoral colloquium, and any other information about the conference location, registration, paper formatting, etc., please consult the Conference’s web site at URL: or  or contact one of the Conference's organizers.